2-14 Internal Architecture
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
The following sections describe the basic architecture and
resources of the processor’s internal caches. For information
about how the system software and hardware control cache
configuration and coherency, see Section 6.2 on page 6-8.
2.3.1 Instruction Cache
The instruction cache has the following characteristics:
■ 16 Kbytes
■ 32-byte line size
■ Four-way, set associative
■ Dual-tagged (linear and physical)
■ Single-clock access
■ Supports 16-byte split-line accesses
■ Requested-word-first line-fill protocol
■ Five predecode bits per instruction byte
■ Round-robin replacement policy
■ Read-only, invalidate on write hit
Instruction-cache accesses can be to any 16 bytes within a sin-
gle 32-byte line or they can be split into two 8-byte accesses
across two contiguous lines.
Split-line fetches can provide instructions from sequential
lines in a single clock. This keeps decode logic supplied with a
steady stream of bytes. Instruction fetches can read any 16
bytes of a single line or—in a split-line fetch—the high 8 bytes
of the first line and the low 8 bytes of the next sequential line
(index + 1 as determined by the A4 address bit), starting on
either an odd or even line.
Instruction-cache lines have only two coherency states (valid
or invalid) rather than the four MESI (modified, exclusive,
shared, invalid) coherency states of data-cache lines. Only two
states are needed because these lines are only read, never writ-
ten. In addition to holding instructions, each instruction-cache
line holds 5 predecode bits per instruction byte. The informa-
tion contained in these bits is described in Section 2.1 on page
2-3.
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