AMD K5 User Manual

2-26 Internal Architecture
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Snoop Writeback
Buffer
In addition to the replacement and invalidation writeback
buffer, the processor also has a 1-entry, 32-byte-wide snoop
writeback buffer in the bus interface unit that is used for
writebacks due to one of the following:
■ Internal snoop during an instruction-cache read miss
■ External inquire cycle in which the INV signal is asserted
A modified data-cache line can be replaced in parallel with a
snoop-hit invalidation to a modified line because the write-
backs go to separate buffers.
2.4 Memory Management Unit (MMU)
The MMU supports standard x86 demand-paged virtual memo-
ry by translating linear addresses to physical addresses. To
speed this process, the most recently accessed address transla-
tions are stored in one of two translation lookaside buffers
(TLBs), one for mapping 4-Kbyte pages and another for map-
ping 4-Mbyte pages. Mappings to 4-Kbyte and 4-Mbyte pages
can be intermixed in a given page directory, the base of which
is pointed to by the contents of control register 3 (CR3).
During memory accesses, the MMU receives a linear address
and searches the TLBs for a corresponding physical address. If
found, the physical address is passed to the physical tag direc-
tory for a validity check. If the physical address is not present
(a TLB miss), the MMU searches the page directory and page
tables in memory. If found, the MMU loads the translation into
the appropriate TLB. If not found, the processor generates a
page fault.
2.4.1 Storage Model
The AMD-K5 processor always observes the strongly ordered
memory-write model. All writes—whether to cache, memory, or
I/O—are performed in program order, regardless of the state
of the External Write Buffer Empty (EWBE) input signal. The
only effect of EWBE on writes is to hold additional writes off
when the signal is negated. In particular, assertion of EWBE
does not permit the AMD-K5 processor to observe a weakly
ordered memory-write model, in which writes to cache may

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm