AMD K5 User Manual

A-2
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
A.1 Bus Signals
A.1.1 Signal Comparison
Table A-1 compares the signals on the Pentium processor with
those on the AMD-K5 processor, showing which signals are sup-
ported on each processor.
Table A-1. AMD-K5 and Pentium Processor Signal Comparison
Signal
Pentium
(735\90,
815\100)
AMD-K5 Function
A20M
x x Address Bit 20 Mask
A31–A3 x x Address Bus
ADS
x x Address Strobe
ADSC
x x Address Strobe
AHOLD x x Address Hold
AP x x Address Parity
APCHK
x x Address Parity Check
APICEN x APIC Enable (High during RESET)
PICD1 x PIC Data 1
BE7
–BE0 x x Byte Enables
Flush(4) x Dual-Processor Flush
APICID3–APICID0 x APIC ID (during reset)
BF (BF1–BF0) x x Bus-to-Core Frequency Ratio
BOFF
x x Bus Backoff
BP3–BP2 x Breakpoint 3 to 2
BP1–BP0/
PM1–PM0
x
Breakpoint 1 to 0 or
Performance Monitor 1 to 0
BRDY
x x Burst Ready
BRDYC
x Drive-Strength Control (during RESET)
x x Burst Ready
BREQ x x Bus Request
BUSCHK
x x Drive-Strength Control (during RESET)
xxBus Check
CACHE
x x Cacheable Cycle

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm