AMD K5

Bus Signals A-3
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
CLK x x System Clock (5 V-tolerant)
CPUTYP x Primary or Secondary Processor
D/C
x x Data or Code Cycle
D63–D0 x x Data Bus
D/P
x Dual or Primary Processor Cycle
DP7–DP0 x x Data Parity
DPEN
x Dual Processor Present (during RESET)
PCID0 x PIC Data 0
EADS
x x External Address Strobe
EWBE
x x External Write Buffer Empty
FERR
x x Floating-Point Error
FLUSH
x x Float-Test Mode (during RESET)
x x Writeback and Invalidate Caches
FRCMC
x x Functional Redundancy Checking Master/Checker
HIT
x x Inquire Hit
HITM
x x Inquire Hit to Modified Line
HLDA x x Hold Acknowledge
HOLD x x Hold
IERR
x x Internal Error
IGNNE
x x Ignore Numeric Error
INIT
x x Execute BIST (during RESET)
x x Initialize (warm start)
INV x x Invalid or Shared After Inquire Cycle
KEN
x x Cache Enable
LINT0/INTR
x Local Interrupt 0 (APIC enabled)
x x Maskable Interrupt
LINT1/NMI
x Local Interrupt 1 (APIC enabled)
x x Non-Maskable Interrupt
LOCK
x x Locked Cycle
M/IO
x x Memory or I/O Cycle
NA
x x Next (pipelined) Address
PBGNT
xPrivate Bus Grant
Table A-1. AMD-K5 and Pentium Processor Signal Comparison (continued)
Signal
Pentium
(735\90,
815\100)
AMD-K5 Function