AMD K5 User Manual

Clock Control 6-37
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
6.4.3 Stop Grant State
The assertion of STPCLK causes the processor to enter the
Stop Grant state. The processor can enter the Stop Grant state
from the normal operating modes (Real, Protected, or Virtual-
8086), SMM, or the Halt state.
When STPCLK is negated, the processor returns to the mode
from which it entered. If the processor entered the Stop Grant
state from the Halt state, negation of STPCLK returns the pro-
cessor to the Halt state. Otherwise, negation of STPCLK or
assertion of RESET returns the processor to the normal operat-
ing mode or SMM, from which it entered. If INIT is asserted in
the Stop Grant state, the signal is latched and acted upon after
STPCLK is negated. No processor registers are saved before
entering the Stop Grant state because the processor returns to
the next unexecuted instruction in program order when it
returns to its prior operating mode.
Within the Stop Grant state (as in the Halt state) the majority
of the processor’s internal clock distribution and all internal
pullup resistors are disabled. However, its phase-lock loop still
runs, its key internal logic is still clocked, most of its inputs
and outputs retain their last state (except D63–D0 and DP7–
DP0 which are floated), and it still responds to input signals.
6.4.4 Stop Grant Inquire State
An inquire cycle driven while the processor is in the Halt or
Stop Grant state causes the processor to transition to the Stop
Grant Inquire state. As for inquire cycles driven from any
other state, system logic must assert AHOLD, BOFF, or HOLD
to obtain the address bus before driving EADS, INV, and the
inquire address.
The processor responds normally to an inquire cycle by driving
HITM and/or HIT and performing any necessary cache-state
transition. If HITM is asserted, the processor drives a normal
writeback (immediately if AHOLD is asserted, or delayed if
BOFF or HLDA is asserted) and returns to the state from which
it entered the Stop Grant Inquire state in the clock in which it
negates HITM. If HITM is not asserted, the processor returns
from the Stop Grant Inquire state to the state from which it
entered, two clocks after EADS.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm