AMD K5 User Manual

5-186 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Figure 5-24B. Cache-Writeback and Invalidation Cycle (WBINVD Instruction) Part 2
CLK
A31–A3
ADS
BE7–BE0
BRDY
CACHE
D/C
D63–D0
KEN
LOCK
M/IO
W/R
CLK
Cache Writeback and
invalidation special cycle
Cache invalidation
special cycle

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm