AMD K5 User Manual

Cache Organization and Management 2-19
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Table 2-2. Cache States for Read and Write Accesses
Type
Tags
1
Cache State
Before Access
5
Access
Type
2
Cache State After Access
MESI State
5
Writeback-
Writethrough
State
Cache Read
Read Miss Linear
invalid single read invalid invalid
invalid
3
(cache-
able)
burst read (line
fill)
shared or
exclusive
4
writethrough or
writeback
4
Read
Hit
Linear
shared — shared writethrough
exclusive — exclusive writeback
modified — modified writeback
Cache
Write
Write Miss Linear invalid single write invalid invalid
Write Hit Linear
shared
cache update
and single write
shared or
exclusive
4
writethrough or
writeback
4
exclusive or
modified
cache update modified writeback
Notes:
1. Linear tags are masked by A20M, physical tags are not.
2. Single read, single write, cache update, and writethrough = 1 to 8 bytes. Line fill = 32 bytes.
3. If CACHE
and KEN are Low.
4. If PWT is Low and WB/WT
is High.
5. MESI state is stored in the physical tags. Instruction-cache state consists only of valid (shared) or invalid, and there are no write-
related states.
— Not applicable or none.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm