AMD K5 User Manual

2-1
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
2
Internal Architecture
The RISC design techniques used in the processor’s internal
architecture account, in large part, for its high performance.
The following sections summarize the processor’s execution
pipeline behavior, the hardware aspects of the internal instruc-
tion cache and data cache, and the hardware aspects of mem-
ory management.
Figure 2-1 shows the major logic blocks that make up the inter-
nal architecture. The blocks are organized in the figure by
stages of the processor’s execution pipeline, which are listed
vertically on the right side of the figure. The blocks are
explained throughout the section that follows.
In this chapter, the terms clock and cycle refer to processor-
clock cycles. If bus-clock cycles or bus cycles are discussed,
they are explicitly named. Processor-clock cycles occur at a
multiple of bus-clock (CLK) cycles, as determined by the BF
input signal(s) and processor model number.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm