Branch Tracing 7-17
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Enabled breakpoints slow the processor somewhat. When a
data breakpoint is enabled, the processor disables its dual-
issue load/store operations and performs only single-issue load/
store operations. When an instruction breakpoint is enabled,
instruction issue is completely serialized.
7.5.3 Debug Compatibility with Pentium Processor
The differences in debug functions between the AMD-K5 and
Pentium processors are described in Section A.7 on page A-15.
7.6 Branch Tracing
Branch tracing is enabled by writing bits 3–1 with 001b and set-
ting bit 5 to 1 in the Hardware Configuration Register
(HWCR), as described in Section 7.1 on page 7-3. When thus
enabled, the processor drives two branch-trace message spe-
cial bus cycles immediately after each taken branch instruc-
tion is executed. Both special bus cycles have a BE7–BE0
encoding of DFh (1101_1111b). The first special bus cycle iden-
tifies the branch source, the second identifies the branch tar-
get. The contents of the address and data bus during these
special bus cycles are shown in Table 7-4.
The branch-trace message special bus cycles are different for
the AMD-K5 and Pentium processors, although their BE7–BE0
encodings are the same.
To Next Page
Loading...
