AMD K5

3-4 Software Environment and Extensions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
3.1.1 Machine-Check Exceptions
Bit 6 in CR4, the machine-check enable (MCE) bit, controls
generation of machine-check exceptions (12h). If enabled by
the MCE bit, these exceptions are generated when either of
the following occurs:
■ System logic asserts BUSCHK to identify a parity or other
type of bus-cycle error
■ The processor asserts PCHK while system logic asserts PEN
to identify an enabled parity error on the D63–D0 data bus
Whether or not machine-check exceptions are enabled, the
processor does the following when either type of bus error
occurs:
■ Latches the physical address of the failed cycle in its 64-bit
machine-check address register (MCAR)
■ Latches the cycle definition of the failed cycle in its 64-bit
machine-check type register (MCTR)
Software can read the MCAR and MCTR registers in the excep-
tion handling routine with the RDMSR instruction, as
described in Section 3.3.5 on page 3-33. The format of the regis-
ters is shown in Figure 3-8 on page 3-25 and Figure 3-9 on page
3-26.
If system software has cleared the MCE bit in CR4 to 0 before
a bus-cycle error, the processor attempts to continue execution
without generating a machine-check exception, although it still
latches the address and cycle type in MCAR and MCTR as
described above.