5-52 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.16 CLK (Bus Clock)
Input
Summary CLK, in conjunction with the state of BF at RESET, determines
the frequency of the processor’s internal clock.
Sampled The processor always samples CLK. The clock must have
begun oscillating prior to the assertion of RESET during
power-up.
Details All processor signals are driven and sampled relative to the ris-
ing edge of CLK, except the edge-triggered interrupts FLUSH
and SMI, which are sampled on the falling edge of CLK.
The processor’s internal clock runs at a multiple of CLK that is
determined by the state of the BF input(s) during RESET. A
digital phase-locked loop generates the internal clock from
CLK.
Power consumption can be reduced to its minimum when sys-
tem logic turns CLK off. The processor enters its Stop Clock
state when system logic asserts STPCLK (thus entering the
Stop Grant state) and subsequently turns CLK off (thus enter-
ing the Stop Clock state). In the Stop Clock state, the proces-
sor’s phase-lock loop and I/O buffers are disabled, except for
the I/O buffers on CLK and the TAP signals. While the proces-
sor is in the Stop Clock state, system logic should not change
the state of any signals other than CLK without first restarting
CLK. When CLK is restarted, the processor returns to the Stop
Grant state and responds to inputs in the next clock, but can-
not drive bus cycles until its phase-lock loop is synchronized.
The latter takes several clocks (see the data sheet for this spec-
ification). For details on STPCLK and the Stop Clock state, see
page 5-122.
While the processor operates with the Test Access Port (TAP),
all TAP events are timed relative to TCK rather than to CLK.
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