AMD K5 User Manual

Signal Descriptions 5-133
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.56 WB/WT (Writeback or Writethrough)
Input
Summary WB/WT, together with PWT, specifies the data-cache MESI
state of cacheable read misses and write hits.
Sampled The processor samples WB/WT in the same clock as the first
BRDY of a bus cycle or NA, whichever comes first.
WB/WT is sampled during memory reads and writes, including
writebacks, in the normal operating modes (Real, Protected,
and Virtual-8086) and SMM, and when PRDY is asserted. WB/
WT is not sampled during I/O cycles, locked cycles, special bus
cycles, or interrupt acknowledge operations; or during the
Shutdown, Halt, Stop Grant, or Stop Clock states; or while
BOFF, HLDA, RESET, or INIT is asserted. While AHOLD is
asserted, WB/WT is sampled only to complete a bus cycle
begun before the assertion of AHOLD.
Details Lines in the shared MESI state are said to be in the
writethrough state. Those in the exclusive or modified MESI
state are said to be in the writeback state. When a write access
either misses the data cache or hits a shared line in the data
cache, the processor drives a 1-to-8-byte write cycle (called a
writethrough) on the bus. When an inquire cycle, internal
snoop, FLUSH operation, or WBINVD instruction hits a modi-
fied line in the data cache, the processor drives a 32-byte burst
write cycle (called a writeback) on the bus. Table 2-2 on page 2-
19 shows the relationships between cache accesses,
writethroughs, and writebacks.
WB/WT and PWT determine the MESI state of a cache line
after a read miss (and resulting cache-line fill) or a write hit.
During read misses, these two signals are interpreted along
with the states of the CACHE output and the KEN input. Dur-
ing write hits, WB/WT and PWT alone determine the resulting
MESI state of a cache line. Tables 5-17 and 5-18 shows the rela-
tionship between WB/WT and PWT for reads (Table 5-17) and
writes (Table 5-18). If WB/WT is Low or PWT is High during a
read miss or write hit, the accessed line is cached in, transi-
tions to, or remains in the shared state after the read or write.
If PWT is Low and WB/WT is High, the accessed line is cached
in, transitions to, or remains in the exclusive state after a read
miss or the first write hit to that line. If the line transitions to

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm