AMD K5 User Manual

6-16 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
3. The processor responds with HITM to system logic.
4. System logic asserts BOFF to the requesting master. (HITM
from the processor can be used to generate BOFF.)
5. The other master negates BOFF to the processor so that the
processor can write back its modified line to main memory
and the shared L2 cache.
Figure 6-3. BOFF Example
A configuration in which both caching masters were on oppo-
site sides of a shared L2 look-through cache would have some-
what similar operations, except that the L2 cache controller
would do much of the signalling ascribed to system logic in Fig-
ure 6-3.
System Bus
Writeback
Processor Bus
EADS
AMD-K5
Processor
BOFF
Other
Caching
Master
Look-Aside
L2 Cache
System
Logic
Main
Memory
BOFF
HITM
1
2
5
3
4

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm