Signal Descriptions 5-65
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.23 FLUSH (Cache Flush)
Input
Summary FLUSH causes the processor to writeback (if necessary) and
invalidate each line in its data and instruction caches. The pro-
cessor generates a flush-acknowledge special bus cycle at the
end of the entire operation. The signal is also used to invoke an
output-float test at RESET.
Sampled and
Acknowledged
The processor samples FLUSH every clock and recognizes it at
the next instruction boundary. FLUSH is a falling-edge-trig-
gered interrupt and is latched when sampled. When FLUSH is
recognized, the processor acknowledges it by driving a flush-
acknowledge special bus cycle after all modified lines in the
data cache are written back and after all lines in both caches
are invalidated.
FLUSH is sampled during memory cycles (including cache
writethroughs and writebacks), cache accesses, I/O cycles,
locked cycles, special bus cycles, and interrupt acknowledge
operations in the normal operating modes (Real, Protected,
and Virtual-8086) and in SMM; or in the Shutdown, Halt, or
Stop Grant states; or while AHOLD, BOFF, HLDA, or RESET is
asserted. FLUSH is not sampled in the Stop Clock state, or
while INIT or PRDY is asserted.
If asserted at the falling edge of RESET, FLUSH invokes the
processor’s three-state (float) test. System logic can drive the
signal either synchronously or asynchronously (see the data
sheet for synchronously driven setup and hold times).
FLUSH is the third-highest-priority external interrupt. For
details on its relationship to other interrupts and exceptions,
see Section 5.1.3 on page 5-13 and Table 5-3 on page 5-16.
Details FLUSH allows system logic to control the data that the proces-
sor sees during cache accesses after changing operating modes
or data environments. It also provides control for special cache
coherency purposes. For example, FLUSH may be asserted
when the processor enters SMM or in systems running
extended memory managers if there is any change that may
affect physical addresses. Depending on how an L2 cache
serves the processor and other caching devices, system logic
may want to cause the L2 cache to invalidate its same locations
when system logic asserts FLUSH to the processor, or it may
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