AMD K5

5-84 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.32 INTR (Maskable Interrupt)
Input
Summary The assertion of INTR, if enabled by software (unmasked),
causes the processor to acknowledge the interrupt and enter
an interrupt service routine. The routine is specified by the
vector obtained during the acknowledgment.
Sampled and
Acknowledged
The processor samples INTR every clock and recognizes it at
the next instruction boundary. INTR is a level-sensitive inter-
rupt and must be held asserted until recognized. When recog-
nized, the processor acknowledges it by driving an interrupt
acknowledge bus operation (a cycle pair).
INTR is sampled during memory cycles (including cache
writethroughs and writebacks), cache accesses, I/O cycles,
locked cycles, special bus cycles, and interrupt acknowledge
operations in the normal operating modes (Real, Protected,
and Virtual-8086) and in SMM; or in the Halt state. INTR is not
sampled in the Shutdown, Stop Grant, or Stop Clock states; or
while AHOLD, BOFF, or HLDA, RESET, INIT, or PRDY is
asserted.
INTR is the seventh-highest-priority external interrupt. For
details on its relationship to other interrupts and exceptions,
see Section 5.1.3 on page 5-13 and Table 5-3 on page 5-16.
System logic can drive the signal either synchronously or asyn-
chronously (see the data sheet for synchronously driven setup
and hold times).
Details In typical PC systems, maskable interrupts are driven to the
processor on INTR from external interrupt-control logic that
prioritizes the interrupts from several I/O devices. The proces-
sor only recognizes INTR if it is enabled in software by setting
the interrupt flag (IF) in the EFLAGS register to 1.
Upon recognizing an INTR interrupt at the next instruction-
retirement boundary, the processor performs the following
actions, in the order shown:
1. Flush Pipeline—The processor invalidates all instructions
remaining in the pipeline.