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AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
A.3 Bus Mastering Operations (including Snooping)
A.3.1 AHOLD Snoop to Linefill Buffer Prior to or Coincident with the
Establishment of the Cacheability of the Line
An AHOLD snoop to the linefill buffer occurs during a linefill
when the address of the snoop matches the address of the line-
fill. If the snoop happens before or coincident with the estab-
lishment of the cacheability of the line via the KEN pin
sampled with the assertion of NA or BRDY (whichever comes
first), the AMD-K5 processor treats the snoop as a hit, whereas
the Pentium processor treats it as a miss.
This difference applies to the AMD-K5 processor Model 0.
Model 1 of the AMD-K5 processor does not have the difference.
Comments In treating the snoop as a hit, the AMD-K5 processor asserts
the HIT pin and also caches the line as either shared or invalid,
depending on the state of the INV pin. If KEN is sampled inac-
tive, the line is not cached, regardless of the state of the INV
pin.
In treating the snoop as a miss, the Pentium processor negates
the HIT pin and caches the line based on KEN, WB/WT, and
PWT in the same way it does for linefills with no snoop.
The behavior of snoops to the linefill buffer after cacheability
is determined is described in Section A.3.2.
A.3.2 BOFF Asserted before Snoop to Linefill Buffer and after the
Cacheability of the Line is Established
A snoop to the linefill buffer occurs during a linefill when the
address of the snoop matches the address of the linefill. If
BOFF is asserted after the cacheability of the line is deter-
mined via the KEN pin being sampled active (with the asser-
tion of NA or BRDY, whichever comes first) and a snoop to the
linefill buffer occurs with either BOFF or AHOLD or both
asserted, the Pentium processor treats the snoop as a hit,
whereas the AMD-K5 processor may or may not treat it as a hit.
For DCACHE linefills, the AMD-K5 processor treats the snoop
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