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AMD K5 User Manual

AMD K5
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5-158 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0Nov1996
For an AHOLD inquire cycle to be recognized, AHOLD must
have been asserted continuously for two clocks at the time
EADS is asserted. AHOLD and BOFF can be asserted in con-
junction with each other without interfering with EADS recog-
nition, as long as the sampling criteria for at least one of the
signals (AHOLD or BOFF) is met.
Figure 5-9. AHOLD-Initiated Inquire Miss
CLK
A31–A3
ADS
AHOLD
AP
APCHK
BE7–BE0
BRDY
BREQ
D/C
D63–D0
EADS
HIT
HITM
INV
M/IO
W/R
CLK
Read Inquire

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AMD K5 Specifications

General IconGeneral
ManufacturerAMD
ModelK5
Architecturex86
MicroarchitectureK5
Introduction Year1996
Clock Speed75 - 133 MHz
Core Count1
SocketSocket 7
Core steppingSSA/5, 5k86
Voltage3.3V
Transistors4.3 million
L1 Cache8 KB (data) + 16 KB (instruction)
FSB50 MHz to 66 MHz
Process Technology350 nm

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