Bus Cycle Timing 5-147
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Single-Transfer
Misaligned Memory
and I/O Transfers
Figure 5-5 shows a misaligned (split) memory read followed by
a misaligned I/O write. (For a definition of misaligned, see Sec-
tion 5.3.3 on page 5-137.) When the processor encounters a mis-
aligned access, it determines the appropriate pair of bus
cycles—each with its own ADS and BRDY—required to com-
plete the access.
In this example, the first pair of bus cycles represents a mem-
ory read of the doubleword at 800Eh. This access crosses a dou-
bleword boundary, so it is misaligned. The processor first reads
the word at 800Eh, followed by the word at 8010h. The second
pair of bus cycles represents a write of a doubleword to I/O
address 8Eh. This transfer also crosses a doubleword bound-
ary, so it is misaligned. The processor writes the word to I/O
address 90h, followed by the word to I/O address 8Eh.
The AMD-K5 processor performs misaligned memory read,
memory write, and I/O read transfers in the reverse order of
the Pentium processor, but misaligned I/O write transfers are
performed in the same order on both processors. Table 5-20
shows the order. Thus, in this example, the I/O write accesses
the most-significant bytes first followed by the least-significant
bytes, the opposite order from the memory accesses and I/O
reads.
The SCYC (Split Cycle) output has no meaning in unlocked
misaligned transfers. It is only meaningful in locked mis-
aligned transfers.
Table 5-20. Bus-Cycle Order During Misaligned Transfers
Type of Access
First K5
Cycle
Second K5 Cycle
Pentium
Compatible?
Memory Read LSBs MSBs no
Memory Write LSBs MSBs no
I/O Read LSBs MSBs no
I/O Write MSBs LSBs yes
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