AMD K5 User Manual

Control Register 4 (CR4) Extensions 3-3
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Table 3-1. Control Register 4 (CR4) Fields
Bit Mnemonic Description Function
7GPE
Global Page
Extension
Enables retention of designated entries in the 4-Kbyte TLB or
4-Mbyte TLB during invalidations.
1 = enabled, 0 = disabled.
See Section 3.1.3 on page 3-9 for details.
6 MCE Machine-Check Enable
Enables machine-check exceptions.
1 = enabled, 0 = disabled.
See Section 3.1.1 on page 3-4 for details.
4 PSE
Page Size
Extension
Enables 4-Mbyte pages.
1 = enabled, 0 = disabled.
See Section 3.1.2 on page 3-5 for details.
3DE
Debugging
Extensions
Enables I/O breakpoints in the DR7–DR0 registers.
1 = enabled, 0 = disabled.
See Section 7.5 on page 7-16 for details.
2 TSD
Time Stamp
Disable
Selects privileged (CPL=0) or non-privileged (CPL>0) use of
the RDTSC instruction, which reads the Time Stamp Counter
(TSC).
1 = CPL must be 0, 0 =any CPL.
See Section 3.2.3 on page 3-27 for details.
1PVI
Protected Virtual
Interrupts
Enables hardware support for interrupt virtualization in Pro-
tected mode.
1 = enabled, 0 = disabled.
See Section 3.1.5 on page 3-24 for details.
0VME
Virtual-8086
Mode Extensions
Enables hardware support for interrupt virtualization in Vir-
tual-8086 mode.
1 = enabled, 0 = disabled.
See Section 3.1.4 on page 3-12 for details.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm