AMD K5 User Manual

5-24 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.3 ADS (Address Strobe)
Output
Summary The processor asserts ADS to specify the beginning of a mem-
ory or I/O bus cycle, or a cache writeback to memory. The sig-
nal validates the processor’s address and cycle definition
signals and it can be used by system logic to enable accesses to
memory and I/O.
Driven and Floated During processor-initiated bus cycles, the processor asserts
ADS for one clock at the beginning of each bus cycle. During
writeback cycles, whether initiated by the processor or by sys-
tem logic, the processor asserts ADS for one clock as early as
two clocks after the processor asserts HITM. The processor can
assert ADS as early as two clocks after the assertion of BRDY
(thus allowing one idle or dead clock between any two bus
cycles), and one clock after the negation of AHOLD, BOFF, or
HLDA.
ADS is driven during memory cycles (including cache
writethroughs and writebacks), I/O cycles, locked cycles, spe-
cial bus cycles, and interrupt acknowledge operations in the
normal operating modes (Real, Protected, and Virtual-8086)
and in SMM, or while PRDY is asserted. While AHOLD is
asserted, and during the Shutdown, Halt, and Stop Grant
states, ADS is driven only for writebacks that result from
inquire cycle hits. ADS is not driven during the Stop Clock
state, or while BOFF, HLDA, RESET, or INIT is asserted.
The processor floats ADS one clock after system logic asserts
BOFF and in the same clock that the processor asserts HLDA.
Details The processor initiates bus cycles for the purpose of reading
and writing memory or I/O, and for writebacks of modified
cache lines. While the processor controls the bus, or while it is
writing back a modified cache line (whether in control of the
bus or not), ADS defines the beginning of the cycle. In the
clock that it asserts ADS, the processor also begins driving the
several signals that define and qualify the bus cycle, including
A31–A3 (or A31–A5 for writebacks), AP, the cycle definition
signals (D/C, M/IO and W/R), BE7–BE0, BREQ, A20M, CACHE,
LOCK, PCD, PWT and SCYC.
If ADS initiates a cache line fill and all four ways of the cache
that could accommodate the incoming line are filled with valid

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm