AMD K5 User Manual

Signal Descriptions 5-55
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.18 D63–D0 (Data Bus)
Bidirectional
Summary The processor drives and samples up to eight bytes on D63–D0
during memory or I/O accesses. System logic must decode the
source and destination of these transfers using the address bus
and various control signals.
Driven, Sampled, and
Floated
As Outputs: For single-transfer writes (including cache
writethroughs), the processor drives D63–D0 valid from one
clock after ADS until BRDY. For writebacks (the only type of
burst write), the processor drives D63–D0 valid from one clock
after ADS until the first BRDY, and thereafter from one clock
after each BRDY until the next BRDY of the bus cycle.
The processor floats D63–D0 one clock after system logic
asserts BOFF in the clock that the processor asserts HLDA.
As Inputs: While BOFF or HLDA is asserted, the processor sam-
ples D63–D0 with every BRDY of the bus cycle.
D63–D0 is driven or sampled during memory cycles (including
cache writethroughs and writebacks), I/O cycles, locked cycles,
special bus cycles, and interrupt acknowledge operations in
the normal operating modes (Real, Protected, and Virtual-
8086) and in SMM, or while PRDY is asserted. While AHOLD is
asserted, D63–D0 is driven or sampled only to complete a bus
cycle that had been initiated before AHOLD was asserted, or
for inquire cycle writebacks. During the Shutdown, Halt, and
Stop Grant states, D63–D0 is driven only for inquire cycle
writebacks. D63–D0 is not driven or sampled during the Stop
Clock state, or while BOFF, HLDA, RESET, or INIT is asserted.
Details Data is transferred between the processor and memory or I/O
on up to eight bytes of the D63–D0 data bus. The BE7–BE0
byte-enable signals specify the validity of each byte on D63–
D0. Table 5-10 shows the relation between D63–D0 and BE7–
BE0. System logic must interpret BE7–BE0 for data byte vali-
dation during single-transfer memory reads and writes and for
all I/O reads and writes. However, for burst reads (cache line
fills) and writes (cache writebacks)—that is, when the proces-
sor asserts CACHE—the processor expects data to be valid
and will drive valid data on all eight bytes of the data bus with-
out regard to the state of BE7–BE0.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm