5-144 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Single-Transfer
Memory Write
Delayed by EWBE
Signal
Figure 5-3 shows two consecutive memory writes. The first
write fills an external write buffer and the second write is
stalled for three clocks by the negation of EWBE.
For writes, system logic can store the address and data in a
write buffer, return BRDY, and perform the store to memory
later. If the number of outstanding writes exceeds the size of
the write buffer, system logic must negate EWBE to prevent
the processor from sending additional writes until EWBE is
asserted. The advantage of negating EWBE as opposed to not
asserting BRDY is that negating EWBE prevents only write
requests, but not asserting BRDY stalls the bus and prevents
all requests.
More specifically, if EWBE is negated with or after the last
BRDY of a write cycle, the processor will not do any of the fol-
lowing:
■ Write a store-buffer entry to the data cache
■ Write to memory (single-transfer or burst), including locked
write to Accessed (A) bit after TLB load
■ Write to I/O (OUTx)
■ Execute the following instructions:
MOV to CR0
MOV to CR4, including during a task switch
WBINVD
INVLPG
CPUID
■ Respond to the following instructions:
FLUSH
SMI
■ Respond to any other interrupts or exceptions that cause a
write to memory, such as pushing state onto the stack or set-
ting the Accessed bit in a segment descriptor. This may
include the BUSCHK, NMI, and INTR interrupts.
For more details, see the description of EWBE on page 5-62.
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