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Power Saving Features A-13

18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual

A.5.4 SMM Save Area

The contents of any reserved locations are not necessarily the

same between the AMD-K5 and Pentium processors. In addi-

tion, the AMD-K5 and the Pentium processors store the IDT

base at different locations in the SMM save area. The AMD-K5

processor stores the IDT base at offset 7F94h, and the Pentium

processor stores it at offset 7F90h. These locations were previ-

ously reserved but are now documented in current Pentium

processor documentation.

A.5.5 NMI Recognition during SMM

When operating in SMM, an NMI request should not be recog-

nized unless an enabled INTR is encountered. Both the

AMD-K5 and Pentium processors do this correctly, but in

slightly different ways. The Pentium processor takes the NMI

request immediately after recognizing the INTR, but before

executing any instructions from the interrupt handler. The

AMD-K5 processor takes the NMI request upon encountering

the IRET in the interrupt handler. (In fact, the AMD-K5 pro-

cessor unmasks NMI when any IRET is encountered, not just

one associated with INTR.)

Comment With both processors, the Intel recommendation of using a

fake INTR to unmask NMI while in SMM works correctly.

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