Signal Descriptions 5-95
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.36 M/IO (Memory or I/O)
Output
Summary The processor drives M/IO to indicate whether it is accessing
memory or I/O on the bus. The signal is driven at the same time
as the other two cycle definition signals, D/C and W/R. A spe-
cific encoding of D/C, M/IO, and W/R identifies one of several
special bus cycles.
Driven and Floated M/IO is driven and floated with the same timing as D/C. See the
description of D/C on page 5-53.
Details The processor accesses I/O when it executes an I/O instruction
(any of the INx or OUTx instructions). The processor accesses
memory when it fetches instructions or executes an instruction
that loads or stores data. Accesses to memory-mapped I/O ports
appear on the bus as memory accesses.
Only data (not code) can be read or written from the I/O
address space; the cycle definition for an I/O code read (D/C =
0, M/IO = 0, W/R = 0) defines an interrupt acknowledge cycle,
and the cycle definition for an I/O code write (D/C = 0, M/IO =
0, W/R = 1) defines a special bus cycle.
The processor specifies all special bus cycles with D/C = 0,
M/IO = 0, and W/R = 1. The cycles are then differentiated by
BE7–BE0 and A31–A3.
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