AMD K5 User Manual

Signal Descriptions 5-135
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
In single-processor systems with no other caching master, WB/
WT is typically tied High. This allows the processor to cache all
cacheable reads in the exclusive state, and all cacheable writes
update only the cache. In systems with multiple caching mas-
ters, WB/WT can be generated after inquire cycles to all other
caching masters by the logical OR of HIT from all of the mas-
ters. This allows the processor to cache reads in the exclusive or
modified state only if no other master has a copy.
While the writeback configuration usually supports higher per-
formance, the writethrough configuration is required for cer-
tain transitions in the write-once cache protocol. For details on
this protocol, see Section 6.2.6 on page 6-19.
During the Hardware Debug Tool (HDT) mode, WB/WT is only
meaningful for cache write misses (PWT = 0 and WB/WT = 1
transition a shared line to an exclusive line). The signal is not
meaningful during cache read misses in the HDT mode,
because the caches are never filled in the HDT mode.
For more details on data-cache MESI state transitions during
reads, see Table 5-9 on page 5-51 and Section 6.2.2 on page 6-9.
Table 5-18. MESI-State Transitions for Writes
Signal or Event
Result of Cache Lookup
Write Miss
Write Hit
shared
exclusive
or modified
CACHE
, PCD
1
—————
KEN
—————
PWT
2
—1—0—
WB/WT
——01—
Cache Update no yes yes yes yes
Write to Memory
writethrough
(1 to 8 bytes)
writethrough
(1 to 8 bytes)
writethrough
(1 to 8 bytes)
writethrough
(1 to 8 bytes)
no
State After Write
3
— shared shared exclusive modified
Notes:
— Don’t care or not applicable.
1. The PCD bit is negated and CACHE
is asserted during a write hit, but these states do not affect the hit.
2. The PWT bit in the page table entry or CR3.
3. Transition occurs after any write to memory. Lines in shared MESI state are said to be in writethrough state. Those in exclusive or
modified MESI states are said to be in writeback state.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm