AMD K5 User Manual

Cache Organization and Management 2-23
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
If an internal snoop hits its target, the processor does the fol-
lowing:
■ During Instruction-Cache Read Miss—The line in the data
cache, store buffer, or writeback buffer is written back (if
modified) and invalidated, and the instruction-cache read is
performed again. If the data-cache line was modified, a
copy of the writeback data is passed directly to the instruc-
tion cache, thus avoiding a line-fill bus cycle after the write-
back bus cycle.
■ During Data-Cache Read Miss—The line in the instruction
cache, prefetch cache, or line-fill buffer stays valid, and the
data-cache read is performed as a single, non-cacheable
read.
■ During Data-Cache Write Miss—The line in the instruction
cache, prefetch cache, or line-fill buffer is invalidated, the
reorder buffer invalidates all instructions in the pipeline
following the instruction that initiated the snoop, and the
data-cache write is performed.
The AMD-K5 processor, like the 486 processor but unlike the
Pentium processor, requires a jump (near or far) after a self-
modifying write to clear the prefetch cache. However, both the
AMD-K5 and the Pentium processors require a serializing
instruction after self-modifying code whose physical address is
aliased to multiple linear addresses.
2.3.7 Buffers
Several buffers are associated with the instruction and data
caches, as described below.
Line-Fill Buffers The processor has two 16-byte line-fill buffers in the bus inter-
face unit, one of which is used during instruction-cache line
fills and the other during data-cache line fills. The buffer holds
half of the 32-byte burst cycle that the processor drives in
response to a cacheable fetch miss.
Instruction-cache lines are 16 bytes wide. During fetch misses,
the first 16 bytes of the burst go through the prefetch cache to
the instruction cache and/or byte queue. The remaining 16
bytes from the 32-byte burst cycle, if they are not used immedi-
ately thereafter to fill the prefetch cache, are held in a 16-byte
line-fill buffer in the bus interface unit for a possible future

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm