AMD K5 User Manual

5-134 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
the exclusive state, a subsequent write hit to the same line tran-
sitions the line to the modified state. During write hits, the
states of PWT and WB/WT can only change a line from shared
to exclusive; it cannot change an exclusive line to a shared line.
Table 5-17. MESI-State Transitions for Reads
Signal or Event
Result of Cache Lookup
Read Miss
Read Hit
shared exclusive modified
CACHE
, PCD
1
1 —000———
KEN
—1000———
PWT ——1—0———
WB/WT
———01———
Cache-Line Fill
(32 bytes)
no no yes yes yes no no no
State After Read
2
—— shared shared exclusive shared exclusive modified
Notes:
— Don’t care or not applicable.
1. The PCD bit is one determinant of the state of CACHE
.
2. Transition occurs after any line fill. Lines in shared MESI state are said to be in writethrough state. Those in exclusive or modified
MESI states are said to be in writeback state.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm