Hardware Configuration Register (HWCR) 7-3
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
7.1 Hardware Configuration Register (HWCR)
The Hardware Configuration Register (HWCR) is a model-spe-
cific register (MSR) that contains configuration bits that
enable cache, branch tracing, debug, and clock control func-
tions. The WRMSR and RDMSR instructions access the HWCR
when the ECX register contains the value 83h, as described in
Section 3.3.5 on page 3-33. Figure 7-1 and Table 7-1 show the
format and fields of the HWCR.
Figure 7-1. Hardware Configuration Register (HWCR)
Disable Data Cache DDC 7
Disable Instruction Cache DIC 6
Disable Branch Prediction DBP 5
Debug Control DC 3–1
000 Off
001 Enable branch trace usages
Disable Stopping Processor Clocks DSPC 0
87654321031
D
I
C
D
D
C
D
B
P
D
C
D
S
P
C
Reserved
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