Cache Organization and Management 2-17
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
dated, many or all of the cached lines may still be valid, but
accesses miss in the linear tags and go through the MMU to the
physical tags. If an access misses the linear tags but hits in the
physical tags, the processor restores the linear tag using the
linear address for the access. This is called a cache-tag recovery.
The revalidation of the linear tag does not add any additional
time to that of the physical-tag access itself.
The linear tags for both caches are invalidated during physical-
tag invalidation, or when the RESET or INIT input signal is
asserted. The linear and physical tags for both caches are inval-
idated when the FLUSH input signal is asserted or when the
INVD or WBINVD instruction is executed.
2.3.4 Cache-Line Fills
Memory reads that miss in the instruction or data cache gener-
ate read-allocate operations. These begin with an attempt to
find an invalid line in one of the four cache ways for the
accessed index. If an invalid line cannot be found in one of the
four ways for the index, a line is pseudo-randomly selected for
replacement from one of the four ways. Then the processor fills
the line by driving a four-transfer burst cycle on the bus,
aligned on 32-byte boundaries, with the target quadword
(qword) delivered first.
Instruction-cache line fills initiate four 8-byte transfers from
memory (one burst cycle) on the bus. All 32 bytes go through
the prefetch cache (which has two 32-byte lines) to the instruc-
tion cache and byte queue, with x86 instruction predecoding
performed on the fly.
Data-cache line fills also initiate four 8-byte transfers on the
bus. If a shared or exclusive line is being replaced prior to the
line fill, the first two 8-byte qwords fill half of the cache line,
while the accessed data item is simultaneously forwarded
through the load/store unit to the ROB and execution units.
Then the remaining two qwords arrive and fill the other half of
the cache line. When the cache line is completely filled, the
state of the line is updated. If the line being filled is replacing
a modified line, the prior contents of the line are copied to a 32-
byte writeback (copyback) buffer in the bus interface unit
while the new line is being read.
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