Bus Cycle Overview 5-139
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.3.4 Bus Speed and Typical DRAM Timing
The processor can be configured for external bus (CLK) speeds
of 50, 60, or 66 MHz. Main DRAM memory can be built from
Page-mode or EDO (extended data out) DRAM, although faster
memory devices can be used for higher performance.
On a 66-MHz bus, the read cycle time for a DRAM-page hit in
EDO DRAM is 7-2-2-2 (7 clocks for the first transfer and 2
clocks for each remaining transfer) and 10-2-2-2 for a DRAM-
page miss. The read cycle time for a DRAM-page hit in Page-
mode DRAM at 66 MHz is 7-4-4-4 and 10-4-4-4 for a DRAM-page
miss. On a 50-MHz bus, there is no change in timing for EDO
DRAM, but Page-mode DRAM timing becomes 6-3-3-3 for a
DRAM-page hit and 8-3-3-3 for a DRAM-page miss.
5.3.5 Bus-Cycle Priorities
The AMD-K5 processor can support only one on-going bus
cycle at a time—pending bus cycles are not buffered. System
logic maintains the ultimate control over the bus. The proces-
sor asserts BREQ to request control of the bus. System logic
asserts AHOLD, BOFF, or HOLD to take control of the bus.
AHOLD passes control of the address bus to system logic for
use in inquire cycles, but permits completion of in-progress
cycles on the data bus. BOFF forces an in-progress bus cycle to
abort and passes control to system logic. HOLD allows an in-
progress bus cycle to complete before passing control to sys-
tem logic.
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