Control Register 4 (CR4) Extensions 3-5
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
3.1.2 4-Mbyte Pages
The TLBs in the 486 and 386 processors support only 4-Kbyte
pages. However, large data structures such as a video frame
buffer or non-paged operating system code can consume many
pages and easily overrun the TLB. The AMD-K5 processor
accommodates large data structures by allowing the operating
system to specify 4-Mbyte pages as well as 4-Kbyte pages, and
by implementing a four-entry, fully-associative 4-Mbyte TLB
which is separate from the 128-entry, 4-Kbyte TLB. From a
given page directory, the processor can access both 4-Kbyte
pages and 4-Mbyte pages, and the page sizes can be intermixed
within a page directory. When the Page Size Extension (PSE)
bit in CR4 is set, the processor translates linear addresses
using either the 4-Kbyte TLB or the 4-Mbyte TLB, depending
on the state of the page size (PS) bit in the page-directory
entry. Figures 3-2 and 3-3 show how 4-Kbyte and 4-Mbyte page
translation work.
Figure 3-2. 4-Kbyte Paging Mechanism
Linear Address
4-Kbyte
Page
Directory
4-Kbyte
Page
Table
4-Kbyte
Page
CR3
011122131 22
Page Directory
Offset
Page Table
Offset
Page
Offset
PDE
PTE
Byte
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