AMD K5 User Manual

Code Optimization 4-1
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
4
Performance
This chapter provides information to assist fast execution and
details on dispatch and execution timing for x86 instructions.
Throughout the chapter, the terms clock and cycle refer to pro-
cessor clock cycles, not bus clock (CLK) cycles.
4.1 Code Optimization
The code optimization suggestions in this section cover both
general superscalar optimization (that is, techniques common
to both the AMD-K5 and Pentium processors) and techniques
specific to the AMD-K5 processor. In general, all optimization
techniques used for the Pentium processor apply to any wide-
issue x86 processor, but wider-issue designs like the AMD-K5
processor have fewer restrictions.
4.1.1 General Superscalar Techniques
■ Short Forms—Use shorter forms of instructions to increase
the effective number of instructions that can be examined
for decoding at any one time. Use 8-bit displacements and
jump offsets where possible.
■ Simple Instructions—Use simple instructions with hard-
wired decode because they often perform more efficiently.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm