AMD K5 - Features

1-2 Overview
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
1.1 Features
■ Pentium-Processor Standard
• Compatible with the Pentium (735\90, 815\100)
processor 296-pin socket
• Compatible with existing Pentium (735\90, 815\100)
processor support infrastructure and system designs
• Compatible with Pentium, 486, and 386 processor soft-
ware
• Compatible with x86 DOS, Microsoft
®
Windows
®
operat-
ing system, and the large installed base of x86 software
• Compatible with IEEE 854 floating-point standard
• Selectable bus frequencies
• Support for multiprocessing
■ High-Performance Execution
• Six execution units (two ALUs, two load/store, one
branch, one floating-point)
• Up to four instructions issued per processor clock
• Out-of-order issue and completion
• Speculative execution along three predicted branches
• Register renaming
• Data forwarding
• Predecoder converts x86 instructions to single-cycle
RISC operations (ROPs)
• Fast integer multiply (4-cycle, fully pipelined)
• Five-stage pipeline
• Single-cycle cache access
• Zero-delay branching, 3-clock misprediction penalty (of-
ten hidden)
• No mixed-operand-size penalty
• No prefix penalty
• Single-cycle misalignment penalty
• No instruction-pairing requirements for parallel issue
• No pipeline invalidation on segment loads
• Efficient support for 16- and 32-bit code, with mixed op-
erand sizes