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Features 1-3

18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual

■ High-Performance Cache and TLBs

• 16-Kbyte instruction cache supports split-line access

• 8-Kbyte, dual-ported data cache with MESI cache coher-

ency protocol

• Dual-tagged (both linear and physical tags)

• Inquire cycles run in parallel with program cache access

• 4-Kbyte TLB (128 entries) and 4-Mbyte TLB (4 entries)

■ Extended Features

• Control Register 4 (CR4)

• CMPXCHG8B instruction

• CPUID instruction

• Time stamp counter (TSC)

• Machine-Specific Registers (MSRs)

• 4-Mbyte page size

• Global pages held in TLB during flushes

■ Low Power

• Static, 3.3-V design

• System Management Mode (SMM) with I/O trapping

• Low-power halt and stop-clock states

• Compatible with U.S. Department of Energy’s Energy

Star program

• Compatible with Microsoft Advanced Power Manage-

ment specification

■ Extensive Test and Debug Features

• Two built-in self-test (BIST) modes

• Output-Float Test mode

• Cache and TLB testing (tags and data)

• Debug registers, with I/O breakpoint extension

• Branch tracing

• Functional-redundancy checking

• IEEE 1149.1-1990 Test Access Port (TAP) and JTAG

boundary-scan testing

• Hardware Debug Tool (HDT)

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