AMD K5

Bus Cycle Timing 5-151
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
(rather than BRDY) is asserted. KEN and WB/WT are validated
by either NA or BRDY, whichever comes first. NA will not gen-
erate a pipelined cycle in the event that there are no pending
internal cycles.
Figure 5-6. Burst Reads
CLK
A31–A3
ADS
BE7–BE0
BRDY
BREQ
CACHE
D/C
D63–D0
KEN
M/IO
PWT
W/R
WB/WT
CLK
Read Read