Bus Cycle Timing 5-157
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
2. Two clocks after the assertion of BOFF or AHOLD, or one
clock after sampling HLDA asserted when HOLD is used,
assert EADS while driving a cache-line address on A31–A5,
and assert or negate INV. The processor latches the address
when it samples EADS asserted.
3. Wait two clocks, watching for HITM and/or HIT to be
asserted:
If neither HIT nor HITM are asserted at the end of two
clocks, or if only HIT is asserted, the inquire cycle termi-
nates.
If HITM is asserted, a writeback follows and the processor
does not recognize EADS again until the last BRDY of the
writeback. The timing of the writeback depends on whether
AHOLD, BOFF, or HOLD was asserted to gain access to the
bus. If AHOLD was used, the processor begins driving the
four-transfer burst writeback as early as two clocks after
asserting HITM, whether or not AHOLD is still asserted. If
BOFF or HOLD was used, the processor delays the write-
back until just after BOFF or HLDA is negated.
The resulting state of a cache line that is hit by an inquire
cycle depends on the state of the INV signal at the time of the
inquire cycle (see Table 5-11 on page 5-71). If INV is negated,
the line remains in or transitions to the shared state. If INV is
asserted, the line is written back, if modified, and transitions to
the invalid state.
AHOLD-Initiated
Inquire Miss
Figure 5-9 shows a burst read, during which system logic
asserts AHOLD to acquire the address bus for an inquire cycle.
The processor floats the address bus one clock after AHOLD is
asserted, although the data bus continues to return data from
the in-progress burst read. (The processor supports only one in-
progress bus cycle. No pending bus cycles are buffered.) Two
clocks after asserting AHOLD, system logic initiates the
inquire cycle by asserting EADS, driving INV (negated in this
example), and driving the inquire address on A31–A5.
Although the inquire cycle misses the cache (HIT is negated
two clocks after EADS), the processor’s assertion of APCHK
two clocks after EADS indicates that a parity error occurred on
the inquire cycle address. Because of this parity error, system
logic should disregard the result of the inquire cycle and per-
form it again.
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