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5-160 Bus Interface

AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996

AHOLD-Initiated

Inquire Hit to

Modified Line

Figure 5-11 shows the same sequence as in Figure 5-10, but this

time the inquire cycle hits a modified line. As in Figure 5-10,

system logic asserts INV with EADS. Two clocks later, the pro-

cessor asserts both HIT and HITM. A few clocks later the pro-

cessor drives a writeback for the cache line and then

invalidates its cached copy. The processor holds HITM

asserted until one clock after the last BRDY of the writeback.

If system logic holds AHOLD asserted throughout an inquire

cycle and any required writeback, system logic must latch the

inquire cycle address when it asserts EADS. This is required so

that, if the inquire cycle hits a modified line, the address used

for the writeback need not be driven by the processor when

the processor asserts ADS for the writeback. Instead, A31–A5

remains an input-only bus and system logic must use its

latched copy of the inquire cycle address. By contrast, if sys-

tem logic always negates AHOLD before the writeback, the

processor drives the writeback address when it asserts ADS for

the writeback, and system logic need not retain a copy of the

inquire cycle address. While the processor drives the write-

back address, it drives only the beginning address for the 32-

byte transfer on A31–A5. System logic must determine the

remaining addresses as shown in Table 5-21 on page 5-150.

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