6-8 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
The cacheability of SMM memory has both advantages and dis-
advantages. By caching SMM memory, the advantage of faster
repetitive accesses is offset by delays due to overwriting cache
lines that may otherwise be reusable after returning from
SMM. If the program that was running prior to entry into SMM
ran out of the cache, and the same program continued to run
after the return from SMM, the processor would need to refill
the caches with the same information after returning from
SMM. If an SMM routine frequently accesses the same loca-
tions, the delays due to cache refills and writeback-invalidates
may be worthwhile. But if an SMM routine seldom accesses the
same locations, the speed of returning and continuing on with
the prior program might be improved by not caching SMM
memory.
If SMM memory space overlaps main memory space that is
cacheable, FLUSH must be asserted when SMI is asserted so
that memory accesses in SMM do not hit locations cached from
main memory. If SMM memory is to be cacheable, FLUSH
must also be asserted with SMI when entering SMM, and the
SMM service routine must execute the WBINVD instruction to
invalidate the caches just prior to executing the RSM instruc-
tion, which returns the processor from SMM. The use of
FLUSH or WBINVD adds potentially significant time to the
entering and leaving of SMM.
6.2 Cache
Systems with multiple bus masters that share cacheable mem-
ory require methods for controlling access to the bus and con-
trolling the coherency of shared memory. The sections below
summarize certain principles and methods used by system
logic, in concert with software, to maintain the coherency of
the processor’s level-1 (or L1) on-chip caches and optional
level-2 (or L2) external cache.
The internal architecture of the processor’s L1 instruction and
data caches is described in Section 2.3 on page 2-13. The oper-
ating system writes the cache disable (CD) and not-
writethrough (NW) bits in CR0 to enable and disable caching,
independent of hardware. Thereafter, the operating system
may write the PCD and PWT bits in the page directory and
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