AMD K5

6-26 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Table 6-2. SMM State-Save Area Map
Offset (hex) Contents Size (bits) Type
FFFC CR0 32 read-only
FFF8 CR3 32 read-only
FFF4 EFLAGS 32 read/write
FFF0 EIP 32 read/write
FFEC EDI 32 read/write
FFE8 ESI 32 read/write
FFE4 EBP 32 read/write
FFE0 ESP 32 read/write
FFDC EBX 32 read/write
FFD8 EDX 32 read/write
FFD4 ECX 32 read/write
FFD0 EAX 32 read/write
FFCC DR6 (FFFF_CFF3h) 32 read-only
FFC8 DR7 32 read-only
FFC4 TR 16 (upper 16 reserved) read-only
FFC0 LDTR 16 (upper 16 reserved) read-only
FFBC GS 16 (upper 16 reserved) read-only
FFB8 FS 16 (upper 16 reserved) read-only
FFB4 DS 16 (upper 16 reserved) read-only
FFB0 SS 16 (upper 16 reserved) read-only
FFAC CS 16 (upper 16 reserved) read-only
FFA8 ES 16 (upper 16 reserved) read-only
FFA4 I/O Trap Dword 32 (See Section 6.3.6) read-only
FFA0 reserved 32 —
FF9C I/O Trap EIP 32 read-only
FF98 reserved 32 —
FF94 reserved 32 —
FF90 IDT Base 32 read-only
FF8C IDT Limit 16 (upper 16 reserved) read-only
FF88 GDT Base 32 read-only
FF84 GDT Limit 16 (upper 16 reserved) read-only
Notes:
1. Locations marked “reserved” may change in future processors.
2. Writing locations marked as “read-only” has unpredictable results.