AMD K5

6-40 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
6.6 Power-Up Requirements
During power-up, CLK should be toggling and RESET should
be asserted as V
CC
is ramping toward normal operating volt-
age. Figure 6-7 shows this timing. After V
CC
and CLK reach
specification, RESET must be asserted for a minimum of 1 ms
to allow the phase-lock loop to synchronize.
Figure 6-7. V
cc
and CLK
RESET must be asserted
for at least 1 ms after V
CC
and CLK are stable.
CLK
RESET
≥ 1 ms
PWRGOOD
V
CC
at Operating Voltage
V
CC