Memory 6-7
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 6-2. Default SMM Memory Map
System logic controls the cacheability of SMM memory with
KEN in the same way that it controls the cacheability of mem-
ory space. If SMM memory is to be non-cacheable, KEN must
be held negated from when SMI is asserted until SMIACT is
negated. If SMM memory is to be cacheable, KEN must be
asserted for cacheable read cycles.
SMM
State-Save
Area
SMM Base Address (CS)
Service Routine Entry Point
Fill Down
SMM
Service Routine
32-Kbyte
Minimum
RAM
0003_8000
0003_FE00
0003_FFFF
0003_0000
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