Model-Specific Registers (MSRs) 3-25
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
3.2 Model-Specific Registers (MSRs)
The processor supports model-specific registers (MSRs) that
can be accessed with the RDMSR and WRMSR instructions
when CPL = 0. The following index values in the ECX register
access specific MSRs:
■ 00h: Machine-Check Address Register (MCAR)
■ 01h: Machine-Check Type Register (MCTR)
■ 10h: Time Stamp Counter (TSC)
■ 82h: Array Access Register (AAR)
■ 83h: Hardware Configuration Register (HWCR)
The RDMSR and WRMSR instructions are described in Section
3.3.5 on page 3-33. The following sections describe the format
of the registers.
3.2.1 Machine-Check Address Register (MCAR)
The processor latches the address of the current bus cycle in
its 64-bit Machine-Check Address Register (MCAR) when a
bus-cycle error occurs. These errors are indicated either by (a)
system logic asserting BUSCHK, or (b) the processor asserting
PCHK while system logic asserts PEN.
The MCAR can be read with the RDMSR instruction when the
ECX register contains the value 00h. Figure 3-8 shows the for-
mat of the MCAR register. The contents of the register can be
read with the RDMSR instruction.
If system software has set the MCE bit in CR4 before the bus-
cycle error, the processor also generates a machine-check
exception as described in Section 3.1.1 on page 3-4.
Figure 3-8. Machine-Check Address Register (MCAR)
0
63
Physical Address of Last Bus Cycle that Failed
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