AMD K5 User Manual

5-32 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
5.2.7 APCHK (Address Parity Check)
Output
Summary The processor asserts APCHK if an even-parity error occurs on
A31–A5 during an inquire cycle.
Driven The processor drives APCHK for one clock, two clocks after
system logic asserts EADS with an inquire address.
APCHK is driven under the same conditions in which EADS is
sampled: See the description of EADS on page 5-58.
Details System logic can use APCHK to initiate a remedy for the error.
Typical PC systems assert an interrupt such as NMI if a parity
error is detected.
See the description of parity error determination for the AP
input on page 5-31. Systems that do not implement address par-
ity checking should ignore APCHK.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm