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AMD K5 User Manual

AMD K5
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5-182 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0Nov1996
Shutdown Cycle Figure 5-21 shows a shutdown and the special cycle that fol-
lows. The processor enters shutdown when an interrupt or
exception occurs during the handling of a double fault (vector
8), which amounts to a triple fault. When the processor encoun-
ters such a triple fault, it stops its activity on the bus and gen-
erates the special bus cycle for shutdown (BE7–BE0 =FEh).
System logic must respond with BRDY.
System logic must assert NMI, INIT, RESET, or SMI to get the
processor out of the Shutdown state.
Figure 5-21. Shutdown Cycle
CLK
A31–A3
ADS
BE7–BE0
BRDY
CACHE
D/C
D63–D0
INTR
KEN
LOCK
M/IO
W/R
CLK
Shutdown
Occurs
Shutdown
Special
Cycle

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AMD K5 Specifications

General IconGeneral
ManufacturerAMD
ModelK5
Architecturex86
MicroarchitectureK5
Introduction Year1996
Clock Speed75 - 133 MHz
Core Count1
SocketSocket 7
Core steppingSSA/5, 5k86
Voltage3.3V
Transistors4.3 million
L1 Cache8 KB (data) + 16 KB (instruction)
FSB50 MHz to 66 MHz
Process Technology350 nm

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