AMD K5

6-4 System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
6.1.2 Memory-Decoder Aliasing of Boot ROM Space
The processor boots in Real mode at address FFFF_FFF0h.
However, because the boot ROM space must be accessed after
the first far jump in the processor’s Real mode, which gener-
ates 20-bit addresses in the space below 1 Mbyte, the address
decoder typically aliases the 16-Kbyte physical boot ROM
space located between FFFF_FFFFh and FFFF_C000h to the
top of the high memory space, between 000F_FFFFh and
000F_C000h, as shown in Figure 6-1.
This reset-address behavior is due to the special way in which
segment translation is performed in the x86 architecture when
RESET or INIT is asserted. Normally, a Real-mode 16-bit seg-
ment selector is shifted left 4 bits to form the segment base,
and then added to the 16-bit offset to produce a 20-bit address.
Thus, F000:FFF0 in the selector:offset format becomes a seg-
ment base of 000F_0000h added to an offset of 0000_FFF0h,
yielding the physical address 000F_FFF0h. When RESET or
INIT is asserted, however, the left-shift is not done and the
high 16 address bits are all set to 1, yielding the physical
address FFFF_FFF0h. Thereafter, address translation only
begins to work in the normal Real-mode manner when the first
far jump is executed. This jump loads the code-segment regis-
ter with a 16-bit segment selector, and this selector-load causes
the address-translation mechanism to begin working in its nor-
mal Real-mode manner.
The system-logic address decoder must make this behavior
transparent to software by aliasing the physical address
FFFF_FFF0h to the physical address 000F_FFF0h. As stated
above, it normally does this by aliasing the entire 16-Kbyte
block between FFFF_FFFFh and FFFF_C000h to between
000F_FFFFh and 000F_C000h.
6.1.3 Cacheable and Noncacheable Address Spaces
When the instruction or data caches are enabled, the processor
can fill them with any information found in the system-defined
cacheable address space—including code and data for applica-
tion programs, BIOS, the operation system and its system-level
data structures—except that the processor does not fill its
instruction or data caches with page directory or page table