AMD K5 User Manual

5-168 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
HOLD-Initiated
Inquire Hit to
Modified Line
Figure 5-15 shows an example similar to the one in Figure 5-14,
except that the inquire cycle hits a modified line (both HIT and
HITM asserted two clocks after EADS). System logic negates
HOLD in the clock after EADS, and two clocks later (one clock
after HIT and HITM transition) the processor negates HLDA.
As early as one clock after negating HLDA, the processor
asserts ADS to drive the writeback, after which the processor
invalidates its copy of the line.
Figure 5-15. HOLD-Initiated Inquire Hit to Modified Line
CLK
A31–A3
ADS
BE7–BE0
BRDY
CACHE
D/C
D63–D0
EADS
HIT
HITM
HLDA
HOLD
INV
KEN
M/IO
W/R
CLK
Read Inquire Writeback

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm