AMD K5

Bus Cycle Timing 5-145
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 5-3. Single-Transfer Memory Write Delayed by EWBE Signal
CLK
A31–A3
ADS
BE7–BE0
BRDY
D/C
D63–D0
EWBE
M/IO
W/R
CLK
Write Write
Effective
BRDY