5-164 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
BOFF-Initiated
Inquire Hit to
Modified Line
Figure 5-13 shows a burst read interrupted by the assertion of
BOFF for the purpose of an inquire cycle. One clock after sam-
pling BOFF asserted, the processor aborts the burst read and
floats its bus. Two clocks after asserting BOFF, system logic
initiates the inquire cycle by asserting EADS and INV, and
driving the inquire address on A31–A5. The processor asserts
both HIT and HITM two clocks after EADS, thus indicating
that the inquire hit a modified cache line. The writeback can-
not occur while BOFF is asserted, however, because the proces-
sor has floated its data and control outputs.
After BOFF is negated, the processor writes back the modified
cache line, holding HITM asserted until one clock after the last
BRDY of the writeback. Because INV was asserted with EADS,
the cache line is invalidated after its writeback. Then, the pro-
cessor restarts—from the beginning—the aborted burst read.
For a BOFF inquire cycle to be recognized, BOFF must have
been asserted continuously for two clocks at the time EADS is
asserted. AHOLD and BOFF can be asserted in conjunction
with each other without interfering with EADS recognition, as
long as the sampling criteria for at least one of the signals
(AHOLD or BOFF) is met.
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