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2-18 Internal Architecture

AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996

2.3.5 Cache Coherency

The processor’s cache-coherency mechanism is based on real

(non-speculative) state. Everything that accesses main memory

has the same view of that memory, which is never modified

speculatively. The contents of the processor’s data cache are

always real-state. Furthermore, on the AMD-K5 processor,

writes to both memory and the data cache are always done in

program order, irrespective of the state of the EWBE input sig-

nal.

The processor’s data cache implements coherency with the

MESI (Modified, Exclusive, Shared, Invalid) protocol. The

instruction cache, which is read-only, has no write-related

states. The instruction cache implements coherency with only

a valid bit, which in effect works like a shared-invalid subset of

the MESI protocol. The coherency state bits are stored in the

physical tags for each cache. The physical tags can be accessed

by external logic (using inquire cycles) or the processor (for

internal snoops) in parallel with accesses to the linear tag by

programs running on the processor.

Table 2-2 shows all possible cache-line states before and after

program-generated accesses to individual cache lines. The

table includes the correspondence between MESI states and

writethrough or writeback states for lines in the data cache.

Table 2-3 shows all possible cache-line states before and after

cache snoop or invalidation operations performed with inquire

cycles. Together, these tables show all of the conditions for

writethroughs and writebacks to memory.

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