AMD K5 User Manual

System Management Mode (SMM) 6-23
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
■ The WBINVD instruction
Asserting A20M masks Real-mode cache addresses even while
the processor does not control the bus. Thus, if another master
takes control of the bus and causes the assertion of A20M, this
masks cache accesses occurring concurrently in the processor.
However, it does not affect the correct execution of programs,
because linear and physical addresses are identical in Real
mode.
The Pentium processor applies masking only to physical
addresses, not to linear addresses. This difference between the
AMD-K5 and Pentium processors of masking linear vs. physical
addresses is not visible to software because linear and physical
addresses are identical in Real mode, and the AMD-K5 proces-
sor samples A20M only in Real mode.
6.3 System Management Mode (SMM)
SMM is an operating mode entered via an interrupt and per-
formed by an interrupt service routine. It is designed for power
management and other system control activities that can occur
transparently to conventional operating systems like DOS and
Windows. The code and data for SMM are stored in an SMM
memory area that should be separate from main memory.
The processor enters SMM when system logic asserts the SMI
interrupt and the processor acknowledges it with SMIACT, at
which point the processor saves its state and jumps to the SMM
service routine. The processor returns from SMM when it exe-
cutes the RSM (resume) instruction from within the SMM ser-
vice routine. Upon return, the processor picks up where it left
off in its prior operating mode, except that special return
options are provided when the processor enters SMM from the
Halt state or from a trapped I/O instruction, as described in the
sections below.
The sections below summarize the SMM state-save area, entry
into and exit from SMM, and exceptions and interrupts in
SMM. Section 6.1.4 on page 6-5 summarizes memory allocation
and addressing in SMM. The SMI and SMIACT signals are
described on pages 5-116 and 5-121, respectively.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm